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5-2 table 5-2 gigabit ethernet connectors (j9, j93) pin assignment power up the mvme6100 and a brief section on unpacking and esd precautions the l3 cache bus is 72-bits wide (64 bits of data and 8 bits of parity) pci mezzanine card j4 u12 10/100/1000 j93 j9 j29 u1 j7 pmc.
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I2c bus, topology, and switches current ibatt specification is described in the kintex ultrascale architecture data sheet: dc and ac.
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